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MIC5165 dual regulator controller for ddr3 gddr3/4/5 memory termination micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com general description the MIC5165 is a dual regulator controller designed specifically for low-voltage memory termination applications such as ddr3 and gddr3/4/5. the MIC5165 offers a simple, low-cost jedec-compliant solution for terminating high-speed, low-voltage digital buses with a power good (pg) signal. the MIC5165 controls two external n-channel mosfets to form two separate regulators. it operates by switching between either the high-side mosfet or the low-side mosfet, depending on whether the current is being sourced to the load or being sunk by the regulator. designed to provide a universal solution for memory termination regardless of input voltage, output voltage, or load current, the desired MIC5165 output voltage can be programmed by forcing the reference voltage externally to the desired voltage. the MIC5165 operates from an input voltage as low as 0.75v up to 6v, with a second bias supply input required for operation. the MIC5165 is available in a tiny msop-10 package with an operating junction temperature range of ?40c to +125c. data sheets and support documentation can be found on micrel?s web site at: www.micrel.com . features ? input voltage range: 0.75v to 6v ? up to 7a v tt current ? tracking programmable output ? power good signal ? wide bandwidth ? logic-controlled enable input ? requires minimal external components ? ddr3, gddr3/4/5 memory termination ? -40c < t j < +125c ? tiny msop-10 package applications ? desktop computers ? servers ? notebook computers ? workstations ? ddr3 andgddr3/4/5 memory termination ____________________________________________________________________________________________________________ typical application MIC5165 as a ddr3 memory terminati on device for 3.5a application june 2010 m9999-061510-b
micrel, inc. MIC5165 june 2010 2 m9999-061510-b ordering information part number temperature range package lead finish MIC5165ymm ?40 to +125c 10-pin msop pb-free note: msop is a green rohs compliant package. lead fi nish is nipdau. mold compound is halogen free. pin configuration 10-pin msop (mm) pin description pin number pin name pin function 1 vcc bias supply (input): apply 3v-6v to this input for internal bias to the controller. 2 en enable (input): cmos compatible input. logic high = enable, logic low = shutdown. the en pin can be tied directly to vddq or vcc for functionality. do not float the en pin. floating this pin causes the ena ble to be in an undetermined state. 3 vddq input supply voltage. 4 vref reference voltage equal to half of vddq. for internal use only. 5 gnd ground. 6 fb feedback (input): input to the internal error amplifier. 7 comp compensation (output): connect a capacitor and resistor from comp pin to fb pin for compensation of the internal control loop. 8 ld low-side drive (output): connects to the gate of the external low-side mosfet. 9 hd high-side drive (output): connects to t he gate of the external high-side mosfet. 10 pg power good (out put): open drain output.
micrel, inc. MIC5165 june 2010 3 m9999-061510-b absolute maximum ratings (1) vcc to gnd.................................................... ? 0.3v to +7v vddq to gnd ................................................. ? 0.3v to +7v en to gnd ....................................................... ? 0.3v to v cc fb to gnd........................................................ ? 0.3v to v cc vref to gnd................................................. ? 0.3v to v ddq comp to gnd.................................................. ? 0.3v to v cc hd, ld to gnd ................................................ ? 0.3v to v cc pg to gnd ....................................................... ? 0.3v to v cc lead temperature (solde ring 10sec. ) ....................... 260c storage temperature (t s )......................... ? 65c to +150c esd rating (3) (hbm) .................................................................... +2kv (mm) ....................................................................+300v operating ratings (2) supply voltage (v cc ).............................................. 3v to 6v supply voltage (v ddq ) ....................................... 0.75v to 6v enable input voltage (v en )..................................... 0v to v in junction temperature range (t j )...... ? 40c < t j < +125c junction thermal resistance msop-10 ( ja )..............................................130.5c/w msop-10 ( jc )................................................42.6c/w electrical characteristics (4) t a = 25c with vddq = 1.5v; vcc = en = 5v, bold values indicate ?40c t j +125c, unless otherwise specified. see test circuit 1 for test circuit configuration. parameter condition min typ max units vref voltage accuracy -1% 0.5v ddq +1% v sourcing; 100ma to 3a -5 -10 0.4 +5 +10 v tt voltage accuracy ( note 5 ) sinking; -100ma to -3a -5 -10 0.4 +5 +10 mv supply current (i ddq ) en = 1.2v (controller on) no load 25 140 200 a supply current (i cc ) no load 15 22 27 ma i cc shutdown current ( note 6 ) en = 0.2v (controller off); no pg pull-up 0.1 5 a start-up time ( note 7 ) vcc = 5v external bias; en = v in 8 15 30 s enable input regulator enabled 1.2 enable input threshold regulator shutdown 0.3 v enable hysteresis 50 mv v il < 0.2v (controller shutdown) 0.01 en pin input current v ih > 1.2v (controller enable) 5.75 a
micrel, inc. MIC5165 june 2010 4 m9999-061510-b electrical characteristics (4) (continued) t a = 25c with vddq = 1.5v; vcc = en = 5v, bold values indicate ?40c t j +125c, unless otherwise specified. see test circuit 1 for test circuit configuration. power good output threshold, % of v tt from nominal 5 10 15 % power good window hysteresis 2 % power good output low voltage i pg = 2ma (sinking) 100 300 mv power good leakage current pg = en = 5v, fb = vref; switch leakage current to ground 0.01 1.0 a power good startup delay time (note 8 ) 1 2.4 ms power good deglitch ( note 9 ) time after fb voltage has gone outside of pg window 5 10 s driver high-side mosfet fully on 4.8 4.97 high side gate drive voltage high-side mosfet fully off 0.03 0.2 low-side mosfet fully on 4.8 4.97 low side gate drive voltage low-side mosfet fully off 0.03 0.2 v notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling pr ecautions recommended. human body model 1.5k ? in series with 100pf. 4. specification for packaged product only. 5. the v tt voltage accuracy is measured as a delta voltage from the reference output (v tt - v ref ). 6. shutdown current is measured only on the vcc pin. the vddq pin will always draw a minimum amount of current when voltage is applied. 7. start-up time is defined as the amount of time from en = v cc to v hd = 90% of v cc . 8. power good startup delay is defined as the amount of time from en=vcc and v fb is within 10% of ?v ddq to v pg = 90% of v cc (v fb = v ref ), during startup (v fb is the sense of v tt ). 9. power good deglitch is defined as the amount of time from the voltage at fb node going out of pg window (with 10mv overdrive voltage) to pg = low.
micrel, inc. MIC5165 june 2010 5 m9999-061510-b test circuit figure 1. test circuit
micrel, inc. MIC5165 june 2010 6 m9999-061510-b typical characteristics i ddq current vs. temperature 0 20 40 60 80 100 120 140 160 180 200 -40 -20 0 20 40 60 80 100 120 temperature (oc) i ddq current (a) v ddq = 6v v ddq = 2.5v v ddq = 1.35 v v ddq = 0.75v i cc current vs. input voltage 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 33.544.555.56 v cc volt age (v) i cc current (ma) 25c -40 c 125 c i cc current vs. temperature 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 -40 -20 0 20 40 60 80 100 120 temperature (oc) i cc current (ma) v ddq = 1.35v v cc = 5v v ddq = 1.35v v cc = 3v i cc shutdown current vs. v cc voltage 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0123456 v cc voltage (v) i cc _shutdown current (a) 125 c -40 c room temp. i cc shutdown current vs. temperature 0 0.05 0.1 0.15 0.2 0.25 0.3 -40 -20 0 20 40 60 80 100 120 temperature (oc) i cc shutdown current (a) v ddq = 0.75 v v ddq = 1.35v v ddq = 2.5v v ddq = 6v hd prop delay vs. v ddq voltage 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0123456 v ddq volt age (v) hd prop delay (s) 25c -40 c 125 c v tt - v ref vs. load (a) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -3 -2 -1 0 1 2 3 load (a) v tt -v ref (mv) v ddq = 6v v ddq = 2.5v v ddq = 1.35v v ddq = 0.75v i ddq current vs. v ddq voltage 0 25 50 75 100 125 150 175 200 0123456 v ddq volt age (v) i ddq current (a) room temp. -40 c 125 c hd prop delay vs. temperature 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 -40-20 0 20406080100120 temperature (oc) hd prop delay (s) v ddq = 1.35v v ddq = 6v v ddq = 2.5v v ddq = 0.75v
micrel, inc. MIC5165 june 2010 7 m9999-061510-b typical characteristics (continued) v tt - v ref vs. temperature (oc) 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 120 temperature (oc) v tt - v ref (mv) 3v -0.1a -3a
micrel, inc. MIC5165 june 2010 8 m9999-061510-b functional characteristics
micrel, inc. MIC5165 june 2010 9 m9999-061510-b functional diagram figure 2. MIC5165 block diagram
micrel, inc. MIC5165 june 2010 10 m9999-061510-b functional description the MIC5165 is a high-performance linear controller, utilizing scalable n-channel mosfets to provide jedec-compliant bus termin ation. termination is achieved by dividing down the v ddq voltage half, providing the reference (v ref ) voltage. the MIC5165 controls two external n-channel mosfets to form two separate regulators. it operates by switching between either the high-side mosfet or the low-side mosfet, depending on whether the current is being sourced to the load or being sunk by the regulator. vddq the vddq pin on the MIC5165 provides the source current through the high-side n-channel and the reference voltage to the device. the MIC5165 can operate at v ddq input voltages as low as 0.75v. a bypass capacitance will increase performance by improving the source impedance at higher frequencies. vref two resistors divide down the v ddq voltage to provide v ref . the resistors are valued at around 21k ?. a minimum capacitor value of 120pf from v ref to ground is mandatory. vcc v cc supplies the internal circuitry of the MIC5165 and provides the voltage to drive the external n-channel mosfets. a small 1 f ceramic capacitor is recommended for bypassing the vcc pin. fb and comp the feedback (fb) pin provides the path for the error amplifier to regulate v tt . a feedback resistor is recommended and resistor values should not exceed 10k ? . the compensation capacitors should not be less than 40pf. en the MIC5165 features an active-high enable (en) input. in the off-mode state, leakage currents are reduced to microamperes. en has thresholds compatible with ttl/cmos for simple logic interfacing. pg MIC5165 features a power good (pg) output. pg is an open drain output with an active high signal. pg requires a pull-up resistor to vcc.
micrel, inc. MIC5165 june 2010 11 m9999-061510-b application information synchronous dynamic random access memory (sdram) has continually evolv ed over the years to keep up with ever-increasing computing needs. the latest addition to sdram technology is ddr3 sdram. ddr3 sdram is the third gener ation of the ddr sdram family and offers improved power savings, higher data bandwidth and enhanced signal quality with multiple on- die termination (odt) selection. in ddr3 sdram the values of the odt are based on the value of an external resistor. in addition to using this external resistor for setting the odt value, it is also used for calibrating the odt value so that it maintains its resistance value to within a 10% tolerance. to improve signal integrity and support higher frequency operation of memory read/w rite, the jedec committee defined a fly-by termination scheme used with the clocks, the command bus and address bus signals. the fly-by topology reduces simultaneous switching noise (ssn) by deliberately causing flight-time skew between the data and strobes at ev ery dram as the clock, address and command signal s traverse the dimm. the ddr3 sdram uses a programmable impedance output buffer. currently, there are two drive strength settings, 34 ? and 40? . the 40 ? drive strength setting is currently a reserved specification defined by jedec, but available on the ddr3 sdram. figure 3. dynamic oct between stratix iii/iv fpga devices the MIC5165 provides two drive signals, the high-side mosfet acts as a pass element to provide output voltage and low side mosfet acts as pull-down to regulate the output termination voltage (v tt ). an internal error amplifier compares the termination voltage (v tt ) and v ref , controlling two external n-channel mosfets to sink or source current to maintain a termination voltage (v tt ) equal to v ref . these mosfets receive their enhancement voltage from a separate vcc pin on the device. although the general discussion is focused on ddr3, the MIC5165 is also capable of providing bus terminations for ddr, ddr2 and gddr3/4/5. vddq the MIC5165 can operate at v ddq voltages as low as 0.75v. due to the possibility of large transient currents being sourced from this line, significant bypass capacitance will increase per formance by improving the source impedance at higher frequencies. since the reference is simply v ddq /2, perturbations on v ddq will also appear at half the amplitude on the reference. for this reason, low-esr capacitors such as ceramics or os-con are recommended on v ddq . v tt the proper combination and placement of the os-con and ceramic capacitors is important to reduce both esr and esl such that high-current high-speed transients do not exceed the dynamic voltage tolerance requirement of v tt . the os-con capacitors provide bulk charge storage while the smaller ceramic capacitors provide current during the fast edges of the bus transition. using several smaller ceramic capacitors distributed near the termination resistors is typica lly important to reduce the effects of pcb trace inductance. vref a minimum capacitor value of 120pf from vref to ground is required to remove high-frequency signals reflected from the source (refer to figure 4). large capacitance values (>1500pf) should be avoided. values greater than 1500pf slow down v ref and detract from the reference voltage?s ability to track v ddq during high speed load transients. figure 4. MIC5165 as a ddr3 memory termination device for 7a application
micrel, inc. MIC5165 june 2010 12 m9999-061510-b vddq gnd vref 120pf figure 5. v ddq divided down to provide v ref vref can also be manipulated for different applications. a separate voltage source can be used to externally set the reference point, bypassing the divider network. also, external resistors can be added from v ref -to-v ddq or v ref -to-ground to shift the reference point up or down. vcc the vcc voltage range is from 3v to 6v, but the minimum voltage on the vcc pin should consider the gate-to-source voltage of the mosfet and v tt voltage. for example, on a ddr3 compliant terminator, v ddq equals 1.5v and v tt equals 0.75v. if the n-channel mosfet selected requires a gate-source voltage of 2.5v, v cc should be a minimum of 3.25v. v ccmin =v tt +v gs feedback and compensation the feedback provides the path for the error amplifier to regulate v tt . an external resistor must be placed between the feedback and v tt . this allows the error amplifier to be correctly externally compensated. for most applications, a 510 ? resistor is recommended. the comp pin on the MIC5165 is the output of the internal error amplifier. by placing a capacitor and resistor between the comp pi n and the fb pin, this coupled with the feedback resistor, places an external pole and zero on the error amplifier. with a 510 ? feedback resistor, a minimum 220pf capacitor is recommended for a 3.5a peak termination circuit. an increase in the load will require additional n-channel mosfets and/or increase in output capacitance may require feedback and/or compensation capacitor values to be changed to maintain stability. enable en can be tied directly to v ddq or v cc for functionality. do not float the en pin. floating this pin causes the enable circuitry to be in an indeterminate state. power good power good signal output remains high as long as output is within 10% range of regulated v tt and goes low if output moves beyond this range. input capacitance the MIC5165 application operates in the linear region during the steady state cond ition, so there are no switching current pulses from the input capacitor. the application does not require a bulk input capacitor, but using one greatly improves device performance during fast load transients. since output voltage v tt follows the input voltage v ddq attention should be given to possible voltage dips on vddq pin. capacitors with low esr such as os-con and ceramics are recommended for bypassing the input. although a 100 f ceramic capacitor will suffice for most applications, input capacitance may need to be increased in cases where the termination circuit is greater than 1-inch away from the bulk capacitance. output capacitance large, low esr capacitors are recommended for the output (v tt ) of the MIC5165. although low esr capacitors are not required for stability, they are recommended to reduce the effects of high-speed current transients on v tt . the change in voltage during the transient condition will be the effect of the peak current multiplied by the output capacitor?s esr. for that reason, os-con type capacitors and ceramic are excellent choices for this application. os-con capacitors have extremely low esr and a large capacitance-to-size ratio. ceramic capacitors are also well suited to termination due to their low esr. these capacitors should have a dielectric rating of x5r or x7r. y5v and z5u type capacitors are not recommended, due to their poor performance at high frequencies and over temperature. the minimum recommended capacitance for a 3.5a peak circuit is 100 f. output capacitance can be increased to achieve greater transient performance. mosfet selection the MIC5165 utilizes exter nal n-channel mosfets to sink and source current. mosfet selection will be determined by two main characteristics: size and gate threshold (v gs ). mosfet power requirements one of the most important factors to determine is the amount of power the mosfet is going to be required to dissipate. power dissipati on in a ddr3 circuit will be identical for both the high side and low side mosfets. since the supply voltage is divided by half to supply v tt , both mosfets have the same voltage dropped across them. they are also required to be able to sink and source the same amount of current (for either all 0s or all 1s). this equates to each side being able to dissipate the same amount of power. power dissipation
micrel, inc. MIC5165 june 2010 13 m9999-061510-b calculation for the high-side mosfet is as follows: p d = (v ddq ? v tt ) i_source where i_source is the average source current. power dissipation for the low-side mosfet is as follows: p d = v tt i_sink where i_sink is the average sink current. in a typical 3.5a peak ddr3 circuit, power considerations for mosfet selection would occur as follows: p d = (v ddq ? v tt ) i_source p d = (1.5v ? 0.75v) 1.75a p d = 1.3125 w this typical ddr3 application would require the high- side and low-side n-channel mosfets to be able to handle 1.3125 watts each. in higher current applications, multiple n-channel mosfets may be placed in parallel to spread the power dissipation. these mosfets will share current, distributing power dissipation across each device. the maximum mosfet die (junction) temperature limits maximum power dissipation. the ability of the device to dissipate heat away from the junction is specified by the junction-to-ambient ( ja ) thermal resistance. this is the sum of junction-to-case ( jc ) thermal resistance, case- to-sink ( cs ) thermal resistance and sink-to-ambient ( sa ) thermal resistance: ja = jc + cs + sa in our example of a 3.5a peak ddr3 termination circuit, we have selected a d-pack n-channel mosfet that has a maximum junction temperature of 125c. the device has a junction-to-case thermal resistance of 1.5c/w. our application has a maximum ambient temperature of 60c. the required junction-to-ambient thermal resistance can be calculated as follows: d aj ja p tt t where t j is the maximum junction temperature, t a is the maximum ambient temperature and p d is the power dissipation. in our example: d aj ja p tt t w3125.1 c60c125 ja = - w c 52.49 ja = this shows that our total t hermal resistance must be better than 49.52c/w. since the total thermal resistance is a combination of all the individual thermal resistances, the amount of heat sink required can be calculated as follows: sa = ja ? ( jc + cs ) in our example: sa = ja ? ( jc + cs ) ) w c 5.0 w c 5.1( w c 52.49 sa + = - w c 52.47 sa = in most cases, case-to-sink thermal resistance can be assumed to be about 0.5c/w. the ddr3 termination circuit for our example, using two d-pack n-channel mosfets (one high-side and one low-side) will require enough copper area to spread the heat away from the mosfet. in this example to dissipate 1.3w from to-252 package a 2 oz copper of 0.4 in 2 on component side is required. in some cases, airflow may also help to reduce thermal resistance. for different mosfet package refer to manufacturer data sheet for copper area requirements.
micrel, inc. MIC5165 june 2010 14 m9999-061510-b mosfet gate threshold n-channel mosfets require an enhancement voltage greater than its source voltage. typical n-channel mosfets have a gate-source threshold (v gs ) of 1.8v or higher. since the source of the high side n-channel mosfet is connected to v tt , the MIC5165 vcc pin requires a voltage equal to or greater than the v gs + v tt voltage. for example, our ddr3 termination circuit has a v tt voltage of 0.75v. for an n-channel mosfet that has a v gs rating of 2.5v, the v cc voltage can be as min as 3.25v. for an n-channel mosfet that has a 4.5v v gs , the minimum v cc required is 5.25v. it is recommended that the v cc voltage has enough margin to be able to fully enhance the mosfets for large signal transient response. in addition, low gate thresholds mosfets are recommended to reduce the v cc requirements.
micrel, inc. MIC5165 june 2010 15 m9999-061510-b ripple measurements to properly measure ripple on ei ther input or output of a switching regulator, a proper ring in tip measurement is required. standard oscilloscope probes come with a grounding clip, or a long wire with an alligator clip. unfortunately, for high frequency measurements, this ground clip can pick up high-frequency noise and erroneously inject it into the measured output ripple. by maintaining the shortest possible ground lengths on the oscilloscope probe, true ripple measurements can be obtained. this requires the removing of the oscilloscope probe sheath and ground clip from a standard oscilloscope probe and wrapping a non-shielded bus wire around the oscilloscope probe. if there does not happen to be any non-shielded bus wire immediately available, the leads from axial resistors will work. figure 6. low-noise measurement
micrel, inc. MIC5165 june 2010 16 m9999-061510-b pcb layout guideline warning!!! to minimize emi and output noise, follow these layout recommendations. pcb layout is critical to achieve reliable, stable and efficient performance. a ground plane is required to control emi and minimize the inductance in power, signal and return paths. the following guidelines should be followed to insure proper operation of the MIC5165 controller application. ic and mosfet ? place the ic close to the point of load (pol). ? the trace connecting controller drive pins to mosfets gates should be short and wide to avoid oscillations. these oscillations are the result of tank circuit formed by trace inductance and gate capacitance. ? use fat traces to route the input and output power lines. ? signal and power grounds should be kept separate and connected at only one location. input capacitor ? place the input capacitor next. ? place the input capacitors on the same side of the board and as close to the mosfet and ic as possible. ? place a ceramic bypass capacitor next to mosfet. ? keep both the vin and pgnd connections short. ? place several vias to the ground plane close to the input capacitor ground terminal, but not between the input capacitors and mosfet. ? use either x7r or x5r dielectric input capacitors. do not use y5v or z5u type capacitors. ? do not replace the ceramic input capacitor with any other type of capacitor. any type of capacitor can be placed in parallel with the input capacitor. ? if a tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%. ? in ?hot-plug? applications, a tantalum or electrolytic bypass capacitor must be used to limit the over- voltage spike seen on the input supply with power is suddenly applied. output capacitor ? use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. ? phase margin will change as the output capacitor value and esr changes. contact the factory if the output capacitor is different from what is shown in the bom. ? the feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. sensing a long high current load trace can degrade the dc load regulation.
micrel, inc. MIC5165 june 2010 17 m9999-061510-b design example MIC5165 as a ddr3 memory termination device for 3.5a application (vddq and mosfet input separated)
micrel, inc. MIC5165 june 2010 18 m9999-061510-b bill of materials item part number manufacturer description qty. grm21br60j226me39l murata (1) c2012x5r0j226m tdk (2) c1, c2, c3, c4 08056d226mat2a avx (3) 22f, 6.3v, ceramic capacitor, x5r, 0805 4 grm188r60j106me47d murata (1) c1608x5r0j106m tdk (2) c5 06036d106mat2a avx (3) 10f, 6.3v, ceramic capacitor, x5r, 0603 1 grm1885c1h390ja01d murata (1) 39pf, 50v, ceramic capacitor, npo, 0603 c6 c1608c0g1h390j tdk (2) 39pf, 25v, ceramic capacitor, npo, 0603 1 c7 06035c101mat2a avx (3) 100pf, 50v, ceramic capacitor, x7r, 0603 1 c8 grm188r71h391ka01d murata (1) 390pf, 50v, ceramic capacitor, x7r, 0603 1 grm31cr60j476me19l murata (1) c3216x5r0j476m tdk (2) c9, c10 12066d476mat2a avx (3) 47f, 6.3v, ceramic capacitor, x5r, 1206 2 c13 grm188r71h102ka01d murata (1) 1nf, 50v, ceramic capacitor, x7r, 0603 1 c14 grm188r71h103ka01d murata (1) 10nf, 50v, ceramic capacitor, x7r, 0603 1 0603zd105kat2a avx (3) c22, c28 grm188r61a105k murata (1) 1f, 10v, ceramic capacitor, x5r, 0603 1 vj0603a121jxacw1bc vishay (4) c23, c12 06033a121jat2a avx (3) 120pf, 25v, ceramic capacitor, npo, 0603 2 vj0603y221kxacw1bc vishay (4) 220pf, 50v, ceramic capacitor, x7r, 0603 c27 06033c221jat2a avx (3) 220pf, 25v, ceramic capacitor, x7r, 0603 1 c26 tcjb107m006r0070 avx (3) 100f, 6.3v, tantalum capacitor, 1210 1 c24, c11 n.u. 0603 ceramic cap 3 c30, c32, c21 c4532x5r0j107m tdk (2) 100f, 6.3v, ceramic capacitor, x5r, 1812 1 c31 open (2sepc2700m) sanyo (5) 2700f, 2.5v os-con cap 1 cin eee-fpa122uap panasonic (6) 1200f, 10v, electrolytic capacitor, smd, 10x10.2-case 1 l1 cdep105me-1r2mc sumida (7) 1.2h, 21a, inductor, 10.4mmx10.4mm 1 q1 2n7002e(sot-23) vishay (4) signal mosfet, sot-23-6 2 q21, q22 sud50n02-06p vishay (4) low vgs(th) n-channel 20-v (d-s) 1 r1 crcw06031101frt1 vishay dale (4) 510? , resistor, 1%, 0603 1 r2 crcw0603698rfrt1 vishay dale (4) 698? , resistor, 1%, 0603 1 r3 crcw06032002frt1 vishay dale (4) 20k, resistor, 1%, 0603 1 r4 crcw06034752frt1 vishay dale (4) 47.5k, resistor, 1%, 0603 1
micrel, inc. MIC5165 june 2010 19 m9999-061510-b bill of materials (continued) item part number manufacturer description qty. r5 crcw06031003frt1 vishay dale (4) 100k, resistor, 1%, 0603 1 r21 crcw0805510rfkta vishay dale (4) 510? , resistor, 1%, 0805 1 r23, r24 crcw06031k00fkta vishay dale (4) 1k, resistor, 1%, 0603 1 r22 crcw06030000fkta vishay dale (4) 0 ? , resistor, 1%, 0603 1 r25 crcw06031002frt1 vishay dale (4) 10k, resistor, 1%, 0603 1 u1 mic22950yml micrel (8) 10a, 0.4mhz-2mhz, synchronous buck regulator 1 u21 MIC5165ymm micrel (8) dual regulator controller for ddr3 1 notes : 1. murata: www.murata.com . 2. tdk: www.tdk.com . 3. avx: www.avx.com . 4. vishay: www.vishay.com . 5. sanyo: www.sanyo.com . 6. panasonic.: www.panasonic.com . 7. sumida: www.sumida.com . 8. micrel, inc.: www.micrel.com .
micrel, inc. MIC5165 june 2010 20 m9999-061510-b pcb layout recommendations top layer top component layer
micrel, inc. MIC5165 june 2010 21 m9999-061510-b pcb layout recommendations (continued) mid-1 layer mid-2 layer
micrel, inc. MIC5165 june 2010 22 m9999-061510-b pcb layout recommendations (continued) bottom layer bottom silk
micrel, inc. MIC5165 june 2010 23 m9999-061510-b package information 10-pin msop (mm)
micrel, inc. MIC5165 june 2010 24 m9999-061510-b recommended land pattern micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are int ended for surgical impla into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. can nt ? 2010 micrel, incorporated.

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